How does Intel manufacture transistors on a 14 nm scale
The connection between wafers, the new challenge from Intel and TSMC
Everything seems simple and wonderful, the advancement of technology, new products are coming faster for the same price or something above and we all enjoy fights between companies to see who gets our money.
But from that backstage There are hundreds of engineers for every company doing their best to keep this industry alive because remember, if you didn't manage to lose nanometers, performance would be stagnant in a few years, and both AMD and Intel would NVIDIA would need to focus all of its efforts on techniques such as vertical stacking.
Even so, the limit would be reached very quickly and we would go back to the original problem. Hence, the industry is dominated by the best node and architecture. The problem is that the paradigms in the wafers must change from now on.
The connection between wafers, a new bottleneck difficult solution
As we know, the layers of the wafers together with their masks are a problem that the entire industry is trying to solve, especially EUV as a new form of engraving. But when the transistors get smaller and smaller, when the chips get bigger and, above all, more information is processed per second, the way to create the same chips begins to reach its limits.
The 7 nm pre-EUV will be the last to maintain the typical initial material structure for TSMC. In Intel it is represented by 14 nm ++ and in Samsung it will also be its 7 nm without EUV, which keep the rules of the game intact.
The connection layers of the wafers suffer from serious problems in the following lithographic processes, especially between the so-called M0 and M1 . Reducing the nanometer range from now on implies coatings between thinner layers, thinner barriers and metals with lower resistances to ensure the structure of these wafers.
Current wafers use high purity copper for such connections, but although copper has been with us for more than 10 years (130 nm), it is not stable to the nanometers discussed earlier, and engineers are looking for a replacement that has its properties and minimizes their defects.
The first tab to move was Intel, whose 10nm tab is included in its first two layers (the most sensitive to structure and joints) a material also known as cobalt, this material being used in coatings and bonds. Oddly enough, the remaining layers use copper again because of their lower cost and stability, especially in higher layers.
Why has copper become a solution to a problem?
Due to the properties of the material itself, copper has a counterproductive effect on the connections of the wafers as the nanometer reduction progresses: It diffuses with the surrounding materials.
In order to avoid this effect, it was covered with a layer as a barrier which, due to the aforementioned reductions, has become so thin that it is no longer viable. It is about 1 or 2 nm rubens Locations For this material, not solving the copper problem, only alleviating it, and when a manufacturer is faced with a new reduction, perfection equals viability for that node.
A shortage of just a few atoms and the action of the barriers disappear, damaging the structure and performance of the wafer, which is why the precision, as we can see, is so high that it is no longer a method that we have to follow to look for other ways to they don't require that much of a cost, and it has so little future. To that we have to add thermal cycles, copper is heavily dependent on them and electromigration takes its toll.
Electromigration, a fundamental defect elimination effect
The new materials currently being developed are intended not only to replace copper as such, but also to improve the migration of atoms. The limitation in this section is critical as it prevents a wafer from contaminating between layers.
Two poorly insulated layers can undoubtedly spoil not only the affected wafer, but also thousands or millions, since the effect is repeated in each and every one of them. Therefore, the process of creating the structure becomes more and more complex and perfect.
For this reason, two materials are used in the development of lithographic processes, such as the 5 nm from Intel or the 3 nm from TSMC / AMD: cobalt and ruthenium. The main strengths of these two are that they limit any type of migration where they can act as a barrier or ladder.
Cobalt isn't new to the industry as such, but ruthenium isn't the greatest challenge facing engineers. The problem is that, as such, manufacturers are very reluctant and we could almost call them conservative when it comes to change, which results in the industry becoming less and less profitable on the price of wafers.
The battle will turn between necessity and conservatism that can define the lithographic processes of the future. Therefore, the industry generally needs a material that does not require coatings and can do everything that copper has done, that is, has all of its merits and no defects.
Costs are and will remain a problem; there could be segmentation in the wafers
Reluctant to implement changes that have swallowed billions in previous investments, the industry won't stop thinking about the ultimate cost of selling a wafer. Therefore, while they may have to give in to keep progressing, it is speculated that it might be the case that two or more kinds of wafers have been assigned to the same node.
The first and cheapest would try to be the one that uses common materials and patterns and has less innovation. The second could be the one that implements the best materials and the latest interconnection techniques at a higher price and even manages to reduce nanometers even more than its sister wafer.
Today we see something like that with Samsung and its 7 nm and 8 nm respectively, where Koreans can improve the density thanks to certain connections and various smaller optimizations. Logically they offer two different prices for each wafer type, so in the future we can see not only LP, LPP with different transistor types, but also wafers with different densities made in the same way with little difference, segmentation as they call it .
Transistors shrink, but patch cords slow down. When are they a problem?
The so called "interconnect cables" will also have another problem and are just their size. Transistors are shrinking, but transistors remain more or less stable and will be a problem in not too long a time.
The most advanced so far apparently and according to various studies that are published, are there 12 nm with the tonic 18 nm for each of them. This multiplied by millions of cables represents a total area that is too large for 3 nm lithography processes.
The density, and hence the space for more transistors per mm2, can be hindered if the size and scale of the interconnect cables are not improved similarly to these. While there has been some significant progress in this regard, there is no consensus or defining evidence to show any real improvement in this section.
Hence, it is another aspect that the industry has to solve at the same time as the materials. Let's just hope that the price per wafer does not rise and, if possible, fall so that the final prices at least do not rise.
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